1. Field of the Invention
The invention relates to circuits for performing arithmetic and logic operations.
2. Description of the Prior Art
There are a large number of multi-purpose logic circuits, including arithmetic circuits capable of selectively performing various arithmetic operations, and also including arithmetic/logic circuits capable of selectively performing a variety of both Boolean logic operations and arithmetic operations. One such circuit is the Motorola MC 10181. Other known circuits indicative of the state of the art are shown in U.S. Pat. Nos. 3,576,984; 3,584,207; 3,624,373; 3,381,117; 3,909,789; and 3,454,310.
Implementation of the known arithmetic and logic circuits in integrated circuits has resulted in substantial economies to computer manufacturers. The greatest economies have been realized for those integrated circuits, notably memory circuits, which are sufficiently adaptable to the requirements of a large number of users to become "standard" circuits which are produced in great volumes by semiconductor manufacturers, thereby resulting in very low cost per circuit. Unfortunately, arithmetic and logic circuits are not as easily "standardized" as memory circuits; different specialized computers require various implementations of arithmetic and logic circuits suitable to the specialized structure of such specialized computers. Consequently, relatively high engineering and development costs are incurred for arithmetic and logic circuits. Relatively low volumes of such arithmetic logic circuits are manufactured; hence, the costs per circuit are high.
One approach to reducing the engineering and development costs per circuit associated with development of "non-standard" integrated circuits and to increase the manufacturing volumes of such circuits has been to utilize so-called LSI (large scale integrated) "gate arrays." LSI gate arrays are integrated circuits which include a large number of un-interconnected "library functions" or logic cells on one semiconductor chip. Such LSI gate arrays are partially manufactured in large volumes up to the point of but not including providing of interconnection metalization between the many cells or library functions to implement various circuits (such as arithmetic and logic circuits). A particular specialized circuit (such as the arithmetic and logic circuit of the present invention) may then be implemented by providing the interconnections required between the available standard cells or library functions on such a partially manufactured gate array in order to provide the specialized circuit. The required interconnections are provided on the partially manufactured gate array by a "custom" manufacturing operation; this operation is much less costly than a complete design of an integrated circuit chip which implements the specialized circuit. In short, the economies of LSI technology have been achieved for the partially manufactured gate arrays and the engineering costs of the specialized circuit only increase the cost of the above-described interconnection operation.
Of course, to achieve maximum economies, it is desirable to implement the arithmetic and logic function circuit of the invention utilizing as few of the standard cells as possible, so that the remaining unused cells may be utilized to implement other circuitry also required in the computer.
The most advanced of the prior art arithmetic and logic circuits, such as the above-mentioned Motorola MC 10181, utilize emitter coupled logic (hereinafter ECL) gates which produce "wire OR-able" output and output compliment signals. A large number of ECL gates each having at least three inputs, are utilized in the closest prior art arithmetic and logic circuits. Each input of such ECL gates requires a separate bipolar input transistor. Such bipolar input transistors require an unduly large amount of semiconductor chip area, thereby increasing the cost per logic function. Further, when complex circuits are implemented in LSI gate arrays, it is undesirable to have a large number of standard gates or library functions having three or more inputs on the "standard" partially manufactured substrate, because there is a large likelihood that a number of such inputs will be unused for the particular specialized circuits to be implemented on that partially manufactured substrate. Such unused inputs represent unused, area-consuming transistors, which limit the economies potentially achievable to the computer manufacturer by use of LSI technology.
Known arithmetic and logic units which include a plurality of one-bit arithmetic and logic circuits are frequently required to provide an output which indicates whether all of the arithmetic sums are logical "zeros." In such arithmetic and logic units an additional gate is required which logically "ORs" the individual sum bits to provide a "zero result" signal.